The Powerful LPDDR4 & LPDDR3 IC System

Essential Features with Enhanced Options

The TurboCATS III-3200STPIC LPDDR4 and LPDDR3 IC test system brings to the memory semiconductor industry a unique combination of performance and affordability along with an upgradeable system design. 128 devices can be tested in parallel in order to provide a faster production. An optional handler interface allows the test system to communicate to a handler which perform device sorting and binning after testing.

Customization Options:

  • LPDDR4 - supports speeds up to 3200Mbps
  • LPDDR3 - supports speeds up to 1866Mbps
  • Capable of testing up to 128 LPDDR4 and LPDDR3 devices in parallel
  • Number of sites for the chassis can be adjusted according to customers' request
  • Supports None-Cable HiFix that can be integrated with a selection of handlers' interfaces

TurboCATS is pioneering a high performance None-Cable HiFix unit integrated with our high performance TCIII-3200STDRIC (DDR4/3 IC) or TCIII-3200STLPIC (LPDDR4/3 IC) test system. The test system is connected to the IC socket board via TurboCATS' None-Cable HiFix unit, which is cableless to maximize the performance of signal transmission. This ensures that the test system is easy to maintain since the user no longer needs to go through hundreds of cable wires within the unit.

What is None-Cable HiFix?

Speed, signal integrity and costs are the challenges for building a HiFix unit integrated to the automated handler system. The conventional HiFix comes with a large bundle of long cable wires to connect with the HiFix and IC socket boards. It causes signal degradation and timing jitter due to the impedance mismatching, conductor losses, radiation effects, etc. It is also difficult to maintain and repair due to the need to go through a large bundle of cable wires.

Multi-Site Networking

Solutions for your Connected Testing

The TCIII-3200STLPIC (LPDDR4/LPDDR3) IC test system can be networked so the user can test up to 128 devices using one PC to control the entire operation. This gives the customer greater flexibility in terms of increasing testing capacity on an as-needed basis.

Handler Interface (optional)

Solutions for your Memory Testing Business

  • Supports up to 128 DUTs on the LPDDR4/LPDDR3 IC test system
  • Supports both manual and automated handler testing
  • It can be integrated with various handlers with/without the None-Cable HiFix

M6771AD / M6741AD Handler

  • Supports LPDDR4/LPDDR3 IC up to
    64 DUT's or 128 DUT's

HT-3309 Handler

  • Supports LPDDR4/LPDDR3 IC up to
    128 DUT's

Features

Testing Capabilities

  • LPDDR4 - 1600, 1866, 2133, 2400, 2667, 2866, 2933, 3200Mbps
  • LPDDR3 - 1333, 1600, 1866Mbps
  • Clock frequency from 667MHz to 1600MHz

Flexible Configuration

  • Configurable from 6-site to 256-site for parallel testing
  • Proper chassis design to meet various handlers' requirements
  • Supports custom load boards for manual test
  • Supports None-Cable HiFix that can be integrated with a selection of handlers' interfaces
  • Optional environmental tests from low to high temperatures ranging from -30°C to 125°C
  • Optional heat chamber is available

GUI Failure Analysis Tool

  • Graphical Failure display shows Failed Bad ICs and DQ pins' location
  • Error logging location of Row/Column/Blanks/Burst/DQs for analyzing failures
  • Address Scramble / Data Scramble
  • Optional tools include Bit Failure Mapping and Schmoo Plot to display the failed Blanks(s) / DQ bits in the RAM

AC & DC Parametric Tests

  • Supports "Contact open pins" and "Leakage current" with VSIM
  • Supports AC/DC/Idds' parametric tests: Continuity, Leakage, Idds' checking
  • Over 35 industry standard test patterns and user script pattern programming are available
  • Supports SPD programming, Read/Write test, Write-Protect, etc.
  • Auto Timing Calibration calibrates the tester and performs test on different types of ICs

Powerful Integration Tool

Combination of Failures

  • Functional Failure: Cell stuck-at, coupling, neighborhood sensitivity and software error faults
  • Parametric Failure: (AC) Speed timing vs. Vdd threshold, (DC) Leakage and Idds
  • High Temperature Failure: System in high temperature environment

GUI Failure Analysis

Graphical Identification of Failed DQs' Locations

Represents the failed DQ pins' locations graphically. The software uses a graphical display to show the test failures at the hardware level: If the IC fails during the test, there would be indications (displayed in RED) marking the failed pin(s) and signal(s).

Address / Data Logging

Error logging can analyze failures by using address and data information.

Bit Failure Mapping

A tool that helps the user find the failed DQ bits in the RAM by spotting and displaying the corresponding row and column addresses.

Address Scramble

Address Scramble allows users to redefine an address' line logic.

Data Scramble

Data Scramble is based on the input addresses, which determine write data or /data.

Shmoo Plot

A two-dimensional diagram that shows the status of the DQ bits of Memory ICs varying over a range of the user's selected parameters (timing and input voltage level).

Script Code Function (optional)

Script Code Debugger

The customer can use a script programming language to create a customized test pattern. It also supports up to maximum 2048 data patterns. The Script Code function also serves as a powerful compiler/debug tool. It contains a built-in compiler and debugger for Script Code programming that allows the user to monitor the timing waveform of the programming algorithm along with the timing bus transactions. This is all accomplished with the Signal Tap tool.

Specifications: LPDDR4 & LPDDR3

Test Frequency LPDDR3 667Mhz to 933Mhz
LPDDR4 800MHz to 1600MHz
Switching Data Rate LPDDR3 1333Mbps to 1866Mbps
LPDDR4 1600Mbps to 3200Mbps
I/O Interface LPDDR3 1.2V HSUL
LPDDR4 Supports LVSTL
Clock Lines 1 pair per site
Address Depth LPDDR3 15 Rows, 12 Columns, 3 BAs
15X/12Y/3Z per site
LPDDR4 17 Rows, 10 Columns, 3 BAs
17X/10Y/3Z per site
Data Width Supports x 16 / 32 bit IC Device
Termination On-chip, dynamic
Variable Timing Edges tSU/tHD, tAC(tDS/DH), tDQSS, tWD
Programmable Timing tRCD, tRP, tCCD, tRL, tFAW, tWTR, tRAS, tRTP, tRFC, etc.
Control PC Requirements Windows 7 (64 bit) or better, Networking interface
AC Power Source 110-240VAC, 50/60Hz
External PC Requirements
(Recommended)
Executes TCIII-3200IC program to control station operation.
Windows 7 (64 bit) operating system or better, i7-core or better, 8G RAM or better, CD DOM, LAN port x 2, USB port, monitor with 1920x1080 resolution or higher, keyboard, mouse, display card or on-board display

TCIII-3200STLPIC & Heat Chamber (optional)

The heat chamber creates a high temperature testing environment to simulate the accelerated life testing and analyze the behaviors of the module.

Heat Chamber Specifications

Power Supply 220V, 50Hz (90 - 110% of rated voltage)
Power Consumption: Power-up : 15A, 220V
Normal operation : 10A, 220V
Display Method 7 Segment LED Display
Processing value (PV) : Green
Setting value (SV) : Red
Display Accuracy: F.S ±0.5% rdg ±1 digit based on SV or 3°C Max.
Sampling Time 0.5 sec. fixed
Vibration: 0.75mm amplitude at frequency of 10-55Hz in each of X, Y, Z directions for 2 hours
Ambient Temperature -10 - 50°C
Storage Temperature -20 - 60°C
Ambient Humidity 35 - 85% RH
Temperature Range 25°C - 85°C
Recommended Setting Temperature 80°C
Air Input Min. 0.5 MPa - Max. 1.0 MPa
Min. 75 psi - 145 psi
Diameter of Gas Tube 6 mm

Software Screenshots

Main Operating Window

Scrip Code Program

Signal Tap Tool

Shmoo Plot

Test Device

Test Plan

Test List

Security Privilege

TURBOCATS, LTD. RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.