TCIII-2133ST | DDR4 & DDR3 Tester
Built to fit your memory testing needs
To assist manufacturers in their efforts to control costs, TurboCATS introduces the new TCIII-2133ST multi-site test system.
Device characterization and failure analysis tools such as Schmoo plotting and address/data error logging are included on the TCIII-2133ST to assist engineers in their design/debug processes. An optional hot temperature chamber is also available to detect marginal timing and cell storage failures that often occur in high temperature system environments.
With the ability to test 4 modules in parallel and at speeds up to 2133Mbps, the TCIII-2133ST will meet the needs of the engineering group while being the ideal ATE for the production floor as well.
TCIII-2133ST Multi-site Test System
Customizable options available
- DDR4 - 1600Mbps, 1866Mbps, 2133Mbps
- DDR3 - 1066Mbps, 1333Mbps, 1600Mbps, 1866Mbps
- Form factor supports - LODIMM, SODIMM, LRDIMM and custom form factors
High-end ATEs are designed to detect functional and AC/DC parametric failures but do not identify or pinpoint potential in-system failures. Most in-system failures caused by functional and timing compatibility issues that are generated by the system chipset. Many in-system device failures occur during system boot up or during the specific testing operation within a given system.
To effectively perform functional testing and in-system compatibility testing, most memory manufacturers incorporate a costly two (2) step testing process as part of their Standard Operating Procedure (S.O.P.).
One of memory manufacturers' most difficult challenges is finding a cost effective method of testing their products so they can minimize the time to market and field failures/ returns. To facilitate this costly and time consuming process, they must incorporate the two (2) step testing method. Capital expenditures, for the equipment and manpower required to perform this extensive testing, often result in budget overruns for various cost centers.
|DDR4 - 1600Mbps, 1866Mbps, 2133Mbps|
|DDR3 - 1066Mbps, 1333Mbps, 1600Mbps, 1866Mbps|
|Operating clock frequency from 533Mhz to 1067Mhz|
|Standard 4 site module testing, in parallel is available, for a high throughput on production floor|
|Form factor supports: LODIMM, SODIMM, LRDIMM and custom form factors|
|Single adapter supports both unbuffered and registered module testing|
|Supports AC/DC parametric and user script pattern programming|
|Supports SPD programming, read, test and write-protect|
|Over 35 industry standard AC test patterns available to the end user to customize their test lists|
|Error logging up to 8192 locations of Row/Column/BA/Busrt/DQ's|
|Optional Support 12V Power Pin of DDR4 NVDIMM, it provides power supply for charging NVDIMM backup energy storage device. The default DC output value is 10.6V (Max current around 1A)|
|Optional 8 or 16 module testing, in parallel, for high throughput on production floor|
|Optional heat chamber for hot environmental testing from 32°C to 85°C|
|Optional handler interface is available for combining the TCIII-2133ST with an automated handling system|
Heat Chamber Optional
Moving Your Business Forward
Heat Chamber Specifications:
|Power Supply :||220V, 50Hz (90 - 110% of rated voltage)|
|Power Consumption :||Power-up : 15A, 220V
Normal operation : 10A, 220V
|Display Method :||7 Segment LED Display
Processing value (PV) : Green
Setting value (SV) : Red
|Display Accuracy :||F.S ±0.5% rdg ±1 digit based on SV or 3°C Max.|
|Sampling Time :||0.5 sec. fixed|
|Vibration :||0.75mm amplitude at frequency of 10-55Hz in each of X, Y, Z directions for 2 hours|
|Ambient Temperature :||-10 - 50°C|
|Storage Temperature :||-20 - 60°C|
|Ambient Humidity :||35 - 85% RH|
|Temperature Range :||25°C - 85°C|
|Air Input :||Min. 0.5 MPa - Max. 1.0 MPa
Min. 75 psi - 145 psi
|Diameter of Gas Tube :||6 mm|
|Dimensions (LxWxH) :||26.2" (665mm) x 10.4" (265mm) x 37.2" (945mm)|
All memory modules manufacturers want to offer the highest quality product they can at a price that allows them to stay competitive while still making a profit. Profitability are decreased when a manufacturer has to add steps and processes in their manufacturing process. They have found that functional testing alone is not enough to take modules from a tester and then put them in a system to test for possible heat related issues since it is too time consuming and costly.
One of the first things that manufacturers look to in terms of advanced and innovative functional testing is the TurboCATS new TCIII-2133ST series. With the purchase of the optional heat chamber, customers eliminate the extra procedure to do heat related testing while the modules are undergoing functional testing. The ROI for manufacturers is significant when they look at integrating the heat testing process with the functional testing. Improved reliability, customer satisfaction, and increased profits are just a few of the many reasons to rely on the TurboCATS solution.
A cost-effective way to grow your business.
DDR4 technology is quickly evolving to test multiple modules in parallel, which is critical to cost effective memory manufacturing. TurboCATS is offering its new TCIII-2133ST unit that will test 4 modules in parallel with one very important new feature.
The new multi-site units can be networked so you can test 16 modules in parallel using only one PC to control the entire operation. This gives the customer greater flexibility in increasing testing capacity on an as needed basis. They can also add new testers should they require the capacity.
Costs are minimized since no additional staff is required to handle the added capacity. Simply integrate the new unit into the existing network and utilize the PC that is already in place.
Testers are available in 4, 8, or 16 site configurations so TurboCATS can meet all of the user's testing needs while keeping costs to a minimum.
Combination of Failures
- Functional Failure: Cell stuck-at, coupling, neighborhood sensitivity and software error faults.
- Parametric Failure: (AC) Speed timing vs. Vdd threshold, (DC) Leakage and Idd's.
- Hot-Temperature Failure: System high temperature environment.
Bit Failure Mapping
Bit failure mapping is a tool that helps users find the failed DQ bits in the RAM. The corresponding row and column addresses the failed DQ bits, which will be displayed conveniently for the user.
The failed Bank is spotted (Figure 1), then the user can find the location of the failed DQ bit (Figure 2) if the user double-clicks the failed Bank.
Script Code Function Optional
Traditional test systems provide the user with a variety of AC test patterns to use in their testing process. If a customer wanted the capability to generate a proprietary test pattern, they had to purchase a high-end automated test system. For most companies this is cost prohibitive and not a viable option.
TurboCATS introduces a new, revolutionary feature called "Script Code" in its new DDR 3/4 multi-site module testing system, the new TCIII-2133ST. In this system, the customer can use the script programming language to create a customized test pattern. Once the pattern is created, the "Script Code" pattern generator/ compiler is used to compile the code and then generate the new test pattern..
Script Code Debugger
The "Script Code" function also contains a built-in compiler and debugger for the "Script Code" programming, which allows the customer to monitor the timing waveform of the programming algorithm as well as the timing bus transactions. This is all accomplished under the "Signal Tap" tool.
The new pattern is then imported into the test list and gives the customer a customized pattern with AC (tSU, tWD, tSAC, tRCD, tCL, tAL, tWR, tRP, tRC, tREF, tRFC, etc.) and DC (Vdd, Vref) parameters for testing their product. Additionally, the customer can also create a motherboard test pattern algorithm using the "Script Code" function. The new TurboCATS III-2133ST performs the test with no-wait states in the operating system.
Utilizing the "Script Code" function gives the customer a high degree of flexibility in terms of timing bus programming for creating unique Read and Write programming transactions under best and worst case AC parameters scenarios. This can also be used to create a no-wait state bus transaction in the Read to Write cycle.
Enhanced DC (VSIM & ISVM)
1. Voltage Sense and Current Measurement (VSIM)
This will detect shorts on the signal line and detect proper values of resistor packs and discrete resistors to ensure that proper values are used in all places as well as ensuring that they are properly mounted.
2. Current Sense and Voltage Measurement (ISVM)
A pattern that will detect any "open pins" on the contacts between test sockets and DIMM's before functional testing begins. This pattern will also detect any open pins on both passive and memory components on the PCB.
3. System Power Short Protection
4. VREFA / VERFQ
Voltage ref short detection including programmable VREFCA and VREFDQ.
|Test Frequency||DDR3, 533Mhz - 933Mhz
DDR4, 800Mhz - 1067Mhz
|Switching Data Rate||DDR3, 1066Mbps - 1866Mbps
DDR4, 1600Mbps - 2133Mbps
|I/O Interface||DDR3, SSTL-15, Class I & Class II
DDR4, POD12 - 1.2V Pseudo Open Drain I/O
|Clock Lines||3 pairs per site, up to 16 sites|
|Address Depth||DDR3: 16 Rows, 15 Columns, 3 BAs, 16X/15Y/3Z per site, up to 16 sites|
|DDR4: 18 Rows, 15 Columns, 4 BAs, 18X/15Y/3Z per site, up to 16 sites|
|Data Width||72 I/O's per site, up to 16 sites|
|DQS's||Differential & single-ended|
|Control Lines||4 CS's, 2 CLKE, 1 RAS, 1 CAS, 1 WE per site, up to 16 sites|
|Variable Timing Edges||tSU/tHD, tDS/DH, tAC|
|Programmable Timing||tRCD, tCL, tRL, tWL, tAL, tRP, tRFC, tWR, tCWL, etc.|
|SPD Program||Read, Program, Edit, Test, Byte Matching, Serialization, Write Protect, Slot test|
|Min. Control PC Requirement||Windows 7 or better, Networking interface|
|Unit Dimensions (LxWxH)
|17.9" (455mm) x 16.7" (425mm) x 15.3" (390mm)|
|79.2 lbs (36 kg)|
|AC Power Source||110-240VAC, 50/60Hz|
An optional handler interface allows the TCIII-2133ST to communicate with a handler that performs DIMMs sorting and binning after testing.
- Main Operating Window
- Test Device Configuration
- Test Plan
- Chip Scope