DDR4, LPDDR4 up to 2133Mbps / DDR3, LPDDR3 up to 1866Mbps / eMCP

Customizable options available

 
 

Which TurboCATS III-2133IC is right for you?

Taking control of your memory IC testing

 
  • Number of sites for the chassis can be requested by the customers
  • Each test board contains up to 6 sites for x8 device. Each chassis can support up to 16 test boards that have a total of 96 sites for x8 device
  • Each PC can support up to 4 chassis, with a total of 384 sites of x8 devices
 
 

FEATURES:

Test capabilities

 
  • DDR4 -1600Mbps, 1866Mbps, 2133Mbps
  • DDR3 -1333Mbps, 1600Mbps, 1866Mbps
  • LPDDR4 - 1600bps, 1866Mbps, 2133Mbps
  • LPDDR3 - 1333Mbps, 1600Mbps, 1866Mbps
  • LPDDR2 - 667Mbps, 800Mbps, 1066Mbps
  • Clock Frequency from 667 MHz to 1066 MHz
 

eMCP function

 
  • Parallel test on LPDDR+ eMMC to save test time
  • eMMC formatting flow
 

DC & AC Parametric tests

 
  • Supports ISVM (Contact open pins) and VSIM (Leakage current)
  • Continuity, Leakage, Idd's measurement
  • Supports User defines script programming for AC/DC parametric
  • Over 35 industry standard AC test patterns available
  • Auto timing calibration
 

GUI Failure Analysis Tool

 
  • Graphical identification of Failed IC's and DQ's
  • Error logging locations of Row/Column/Blanks/Burst/DQ's
  • Bitmapping display the failed DQ bits in the ICs
  • Supports Address/Data Scrambling function
  • Shmoo Plot shows the status of the DQ bits of ICs in the user-selected parameters
 

Flexible Configuration

 
  • Configurable from 6-site to 512-sites for parallel test
    • Proper chassis design to meet various selective handlers requirement
    • Supports custom load boards for manual test
    • Supports None-Cable HiFix for integrating to selective handler interface
  • Optional environmental test for low and high temperature from -30°c to 125°c
  • Optional heat chamber for hot environmental testing from 32°C to 85°C
 

To assist manufacturers in their efforts to control costs, TurboCATS proudly introduces the new TCIII-2133IC multi-site test system.

High-end ATEs are designed to detect functional and AC/DC parametric failures but do not identify or pinpoint potential in-system failures. Most in-system failures caused by functional and timing compatibility issues that are generated by the system chipset. Many in-system device failures occur during system boot up or during the specific testing operation within a given system. To effectively perform functional testing and in-system compatibility testing, most memory manufacturers incorporate a costly two (2) step testing process as part of their Standard Operating Procedure (S.O.P.).

One of memory manufacturers' most difficult challenges is finding a cost effective method of testing their products so they can minimize the time to market and field failures/ returns. To facilitate this costly and time consuming process, they must incorporate the two (2) step testing method. Capital expenditures, for the equipment and manpower required to perform this extensive testing, often result in budget overruns for various cost centers.

Device characterization and failure analysis tools such as Schmoo plotting and address/data error logging are included on the TCIII-2133ST to assist engineers in their design/debug processes.

 
 
 

eMCP Function (eMMC + LPDDR4 / LPDDR3 / LPDDR2)

Faster Test Time

 
  1.   LPDDR4 / LPDDR3 / LPDDR2 and eMMC are tested in parallel in a single test flow for reduce test time
  2.   DC/AC and Script Code function are supported for the LPDDR4 / LPDDR3 / LPDDR2
  3.   LPDDR2 : 800Mbps, LPDDR3 : 1866Mbps, LPDDR4 : 2133Mbp
  4.   Supports eMMC formatting flow
  5.   Easy to re-configure different types of packages and devices
  6.   Supports manual test and automated handler test
  7.   A turnkey solution is available for testing up up to 128 DUT's in parallel with a cost effective handler
 

 
 
 

Hot Temperature Chamber

An optional hot temperature chamber is also available to detect marginal timing and cell storage failures that often occur in high temperature system environments. The chamber is user programmable and can be set at temperatures ranging from 32°C to 85°C with 2°C resolution.

 
 
 

Multi-site Networking

Better technology is better business

 
 

 
 

Configurable : 6~384 Sites Testing

  • DDR4, LPDDR4 - 2133Mbps
  • DDR3, LPDDR3 - 1866Mbps
 

DDR4 technology is quickly evolving to test multiple modules n parallel, which is critical to cost effective memory manufacturing. TurboCATS is offering its new TCIII-2133ST unit that will test 4 modules in parallel with one very important new feature.

The new multi-site units can be networked so you can test 384 ICs using only one PC to control the entire operation. This gives the customer greater flexibility in terms of increasing testing capacity on an as needed basis. The customer add new testers only when they require the increased capacity.

Costs are minimized since no additional staff is required to handle the added capacity. Simply integrate the new unit into the existing network and utilize the PC that is already in place.

 
 

TCIII-2133IC with Heat Chamber Optional

Heat Chamber is available to be combined with the test system

All memory modules manufacturers want to offer the highest quality product they can at a price that allows them to stay competitive while still making a profit. Profitability are decreased when a manufacturer has to add steps and processes in their manufacturing process. They have found that functional testing alone is not enough to take modules from a tester and then put them in a system to test for possible heat related issues since it is too time consuming and costly.

One of the first things that manufacturers look to in terms of advanced and innovative functional testing is the TurboCATS new TCIII-2133ST series. With the purchase of the optional heat chamber, customers eliminate the extra procedure to do heat related testing while the modules are undergoing functional testing. The ROI for manufacturers is significant when they look at integrating the heat testing process with the functional testing. Improved reliability, customer satisfaction, and increased profits are just a few of the many reasons to rely on the TurboCATS solution.

 

Heat Chamber Specifications:

 
Power Supply : 220V, 50Hz (90 - 110% of rated voltage)
Power Consumption : Power-up : 15A, 220V
Normal operation : 10A, 220V
Display Method : 7 Segment LED Display
Processing value (PV) : Green
Setting value (SV) : Red
Display Accuracy : F.S ±0.5% rdg ±1 digit based on SV or 3°C Max.
Sampling Time : 0.5 sec. fixed
Vibration : 0.75mm amplitude at frequency of 10-55Hz in each of X, Y, Z directions for 2 hours
Ambient Temperature : -10 - 50°C
Storage Temperature : -20 - 60°C
Ambient Humidity : 35 - 85% RH
Temperature Range : 25°C - 85°C
Recommend Setting
Temperature :
80°C
Air Input : Min. 0.5 MPa - Max. 1.0 MPa
Min. 75 psi - 145 psi
Diameter of Gas Tube : 6 mm
Dimensions (LxWxH) : 26.2" (665mm) x 10.4" (265mm) x 37.2" (945mm)
 
 

Combination of Failures

 
  • Functional Failure: Cell stuck-at, coupling, neighborhood sensitivity and software error faults.
  • Parametric Failure: (AC) Speed timing vs. Vdd threshold, (DC) Leakage and Idd's.
  • Hot-Temperature Failure: System high temperature environment.
 
 
 

Bit Failure Mapping

Bit failure mapping is a tool that helps users find the failed DQ bits in the RAM. The corresponding row and column addresses the failed DQ bits, which will be displayed conveniently for the user with the aid of diagrams.

 
 
 

Script Code Function Optional

Traditional test systems provide the user with a variety of AC test patterns to use in their testing process. If a customer wanted the capability to generate a proprietary test pattern, they had to purchase a high-end automated test system. For most companies this is cost prohibitive and not a viable option.

TurboCATS introduces a new, revolutionary feature called "Script Code" in its new DDR 3/4 test system, the new TCIII-2133ST. In this new system, the customer can use the script programming language to create a customized test pattern. Once the pattern is created, the "Script Code" pattern generator/ compiler is used to compile the code and then generate the new test pattern.

The "Script Code" function also contains a built-in compiler and debugger for the "Script Code" programming, which allows the customer to monitor the timing waveform of the programming algorithm as well as the timing bus transactions. This is all accomplished under the "Signal Tap" tool.

 

Script Code Debugger

 

The new pattern is then imported into the test list and gives the customer a customized pattern with AC (tSU, tWD, tSAC, tRCD, tCL, tAL, tWR, tRP, tRC, tREF, tRFC, etc.) and DC (Vdd, Vref) parameters for testing their product. Additionally, the customer can also create a motherboard test pattern algorithm using the "Script Code" function. The new TurboCATS III-2133ST performs the test with no-wait states in the operating system. Utilizing the "Script Code" function gives the customer a high degree of flexibility in terms of timing bus programming for creating unique Read and Write programming transactions under best and worst case AC parameters scenarios. This can also be used to create a no-wait state bus transaction in the Read to Write cycle.

 
 

Handler Interface Optional

TurboCATS Series testers support both manual and automated handler testing. It can be integrated to various handlers with/ without the None-Cable HiFix and support up to 192 DUT's on DDR3 / DDR4 IC, or 128 DUT's on eMCP / LPDDR IC.

M6771AD / M6741AD Handler
  • DDR4 / DDR3 / LPDDR3 / LPDDR2 up to
    64 DUT's or 128 DUT's
HT-3309 Handler
  • LPDDR3 / LPDDR2 / eMCP up to 128 DUT'S
  • DDR3 / DDR4 up to 192 DUT's
 
 
 

AC SPECIFICATIONS:

 
Test Frequency DDR3
DDR4
533Mhz to 933Mhz
800Mhz to 1066Mhz
LPDDR2
LPDDR3
LPDDR4
333Mhz to 533Mhz
533Mhz to 933Mhz
800Mhz to 1066Mhz
Switching Data Rate DDR3
DDR4
1066Mbps to 1866Mbps
1600Mbps to 2133Mbps
LPDDR2
LPDDR3
LPDDR4
667Mbps to 1066Mbps
1066Mbps to 1866Mbps
1600Mbps to 2133Mbps
I/O Interface DDR3 SSTL-15, Class I & Class II
SSTL-135, Class I & Class II
DDR4 POD-12, 1.2V Pseudo Open Drain I/O
LPDDR2 1.2V HSTL Class 1
LPDDR3 1.2V HSUL
Clock Lines 1 pair per site
Address Depth DDR3 16 Rows, 15 Columns, 3 BAs per site
DDR4 18 Rows, 15 Columns, 4 BAs per site
LPDDR2 14 Rows, 10 Columns, 3 BAs per site
LPDDR3 15 Rows, 12 Columns, 3 BAs per site
Data Width 8 I/O; Supports 4 / 8 / 16 / 32 bit IC devices
DQS's Differential
Control Lines DDR3,
DDR4
2 CS's, 2 CLKE, 1 RAS, 1 CAS, 1 WE
LPDDR2 2 CS's, 2 CLKE, 10 CA pins
LPDDR3 2 CS's, 2 CLKE, 10 caPINS, 1 ODT
Termination On-chip, dynamic
Variable Timing Edges tSU/tHD, tWD, tDQSS, tAC
Programmable Timing DDR3,
DDR4
tRCD, tCL, tRL, tWL, tAL, tRP, tRFC, tWR, tCWL, etc.
  LPDDR2,
LPDDR3
tRCD, tRL, tWL, tAL, tRP, tRFC, tWR, etc.
SPD Programming Read, Write, ByteMatching, Write Protect, Slot Test, etc.
eMCP Function: LPDDR +eMMC are tested in parallel and single test flow to save test time
LPDDR2 to 800Mbps, LPDDR3 to 1866Mbps, LPDDR 4 to 2133Mbps
Supports eMMC formatting flow
Min. Control PC Requirement Windows 7 or better, Networking interface
Unit Dimensions (LxWxH)
* Approximate
6-site : 13" (330mm) x 9.1" (230mm) x 12.6" (320mm)
24-site : 27.6" (700mm) x 20.5" (520mm) x 15.3" (390mm)
Unit Weight
* Approximate
6-site : 19.8 lbs (9 kg)
24-site : 132 lbs (60 kg)
AC Power Source 110-240VAC, 50/60Hz
 
 
 

Software Screenshots

  • Main Operating Window

  • Test Device Configuration
 

  • Test Plan

  • Shmoo Plot Dot